This invention relates generally to semiconductor structures and methods for packaging such structures.
As is known in the art, after active semiconductor devices have been formed in a semiconductor chip, in order to protect such devices the chip is encapsulated in packaging material. Also, a seal ring is typically formed in the dielectric layer around the outer edge region of the chip to protect the active devices formed in the inner region of the chip from contaminants.
In a typical fabrication process, a large single crystal of silicon is sliced into wafers which are typically 6 inches to 12 inches in diameter, but only 0.011 inches to 0.024 inches thick. Using vapor deposition and photo-imageable masking technology, alternating layers of aluminum and glass-like PETOS dielectric (Plasma Enhanced TetraEthylOrthoSilicate, commonly called "oxide") are applied to the surface of the wafer. Since these layers are deposited at high temperatures and since the aluminum typically used for electrical interconnect lines and the oxide have very different thermal coefficients (23 ppm/.degree. C. and 0.5 ppm/.degree. C., respectively), a great deal of intrinsic stress is generated when the wafer is cooled to room temperature. After depositing a final passivation layer, typically of silicon nitride, to protect the active circuits previously formed in the wafer, the wafer is sawed apart to singulate the individual dies, or chips. The dies are tested electrically and then installed into a package. The package is typically made of either ceramic (for high power/high cost devices) or plastic (for low power/low cost devices). For plastic packaging, the die is mounted on a die pad portion of a copper lead frame using, typically, an epoxy adhesive and then connected electrically to bond fingers in the leadframe using fine (typically, 0.001 inch diameter) gold bond wires. The leadframe is then encapsulated in, typically, a silica filled, Novolac epoxy molding compound using a transfer molding process.
As noted briefly above, the die fabrication process creates intrinsic stresses in: the dielectric layers (i.e., a silicon dioxide insulating layers used to, inter alia, electrically isolate the electrical interconnect lines); the aluminum electrical interconnect lines; and, the passivation layer on the surface of the die. When the die is encapsulated, additional stresses are generated by the expansion differential between the die and molding compound as the die cools to room temperature. To further complicate the issue, the adhesive bond between the molding compound sometimes fails (i.e., delaminates) which can concentrate forces and stresses on the die's surface. If the stresses are high enough, it is possible for the passivation layer and/or the dielectric layers to crack. Once this has occurred, moisture can penetrate into the aluminum lines which can cause corrosion leading to device failure. More particularly, referring to FIG. 1, these shear stresses in semiconductor chip 10 cause the passivation layer, not shown, over metal interconnect lines 12 to crack and the entire metal interconnect line 12 to be displaced toward the central, inner region 14 of the chip 10 where the active devices 16 are formed. As shown in FIG. 1, the seal ring 18 is formed around the outer periphery of the chip 10 and contact pads 19 are shown disposed between the inner region 14 and the seal ring 18.
One technique suggested to reduce mechanical stresses at the interface between the surface passivation layer and the plastic molding compound is die coating and wafer coating. Such coatings act as mechanical buffer layers with low elastic moduli and high failure strains which deform to accommodate the mechanical property mismatch between the plastic mold compound and the chip. These coatings are used to promote adhesion between the mold compound and the chip surface, However, these coatings add significant cost to the product.